搜索资源列表
小学生加法器设计
- java小应用程序开发，小学生加法器实现，包含友好界面，过程简洁，算法详细。-small application development, students achieve Adder, including friendly interface, simple process, the algorithm in detail.
adder
- 多位数加法 多位数加法 -More than the median more than the median adder adder adder more than the median
adder
- this code written in systemc language and it is a wewest language that important to simulate the system
adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
adder
- 实现各种加法器的功能，包括4位及8位超前进位，4位及8位逐次进位加法-The various adder functions, including four and eight lookahead, 4-bit and 8-bit successive-carry adder
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
32bit-adder
- 用hspice软件写完成的32位加法器,可以完成2个32bit数组的加法运算-32bits adder for hspice
ADT-Adder-2.0
- adt adder for world of warcraft adt files
adder
- 二进制加法器流水灯，发上来给大家看看，互相学期吧-Binary adder water lights, made up for everyone to see, each semester,
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
four-lookahead-adder
- verilog_HDL-四位超前进位加法器,学习资料，可以方便的用-verilog_HDL-four lookahead adder, learning materials, you can easily use
adder
- 一个初学者容易明白的加法器,大家可通过这个学到很多基础知识-a adder easy
Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
adder
- 全加器：Powerpoint课件示例支持，典型组合逻辑原理图输入设计-full adder design with VHDL
ADDER
- 一个简单的加法器的MFC应用程序，同时可以实现浮点数的操作。-A simple adder MFC application, also can realize the operation of floating point Numbers.
VHDL-Carry-Save-Adder
- VHDL CARRY SAVE ADDER 4,8 BIT DATAFLOW 26,32 BIT STRACTURAL DESIGN
Carry-select-Adder-4bit-Behavioral
- CARRY SELECT ADDER 4 BIT BAHAVIOURAL DESIGN
Adder
- VHDL code for 4bit adder and full/half adders