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verilog程序源码，实现两个16bit数乘法，使用booth算法，一种基于状态机实现，分层层次为datapath与controller两个子模块，testBench测试通过
-verilog program source code, and two 16bit multiplication using booth algorithm, based on the state machine implementation, the hierarchical level for the da
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SEQUENTIAL MULTIPLIER IN VERILOG USING BOOTH S ALGORITHM
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利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
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采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
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Booth algorithm multiplier
this project design booth multiplier by verilog language. you can open it by ISE and simulate.
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