搜索资源列表
DigitalWatch
- 用verilog数字钟，并且在ise上验证，可以显示分秒，并且可以对分和秒进行调整-Verilog digital clock, and verified in ise, can display every minute, and you can adjust the minutes and seconds
fuck
- verilog写的数字时钟，可以暂停时间，写入时间，最好用外扩键盘不然程序会跳动！-digital clock verilog to write, you can pause time, write time, the best keyboard or external expansion program to beat!
m-sequence-of-pseudo-random-noise
- 基于verilog 的用于通信系统的m序列伪随机噪声，可综合，我已验证通过。-Based on the verilog for m-sequences of pseudo-random noise of the communication system, can be integrated, I verified through.
verilogUART
- verilog实现的串口实现代码，可以直接复制使用-verilog achieve serial implementation code can be copied directly use
testbench_verilog
- 一些比较优秀的常用的verilog teshbench程序，可以根据需要，少做修改，就可测试自己i的程序-Some of the more outstanding the commonly used the verilog teshbench of procedures needed less modified, can test their i program
beep
- 蜂鸣器（verilog），自己做的实验板，通过调试，能响起美妙的音乐哦-Buzzer (verilog), own experiments board, debugging can be sounded wonderful music oh
addrdecoder
- 可用来做外围设备的地址译码的Verilog程序-Verilog program can be used for address decoding peripherals
pcm
- verilog 的代码，是pcm采编器，经过验证的，可以用，并且附带上testbench文件。-The verilog code pcm editorial, proven, you can use, and comes on the testbench file.
pushbox
- 推箱子游戏的verilog代码编写，下载到 板子上可以实现-The pushbox game Verilog coding downloaded to the board can be achieved
Vending-machine
- 使用verilog语言编写的自动售货机按钮，可以实现简单的售货功能-Vending machines using Verilog language button, you can achieve a simple function of goods sold
verilog_stand_cell_lib
- verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition
gray
- 格雷码，用verilog写的，初学者可以-Gray code, verilog is written, beginners can look
rvp
- 解析verilog代码的perl脚本，解析结果可用于一系列验证自动化-Verilog code parsing perl scr ipt that the analytical results can be used to automate a series of verification
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
SDRAM100M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是100M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 100m, the hope can help you
juzhenjianpan
- verilog写的一个5乘5键盘扫描程序，并可以利用数码管实现对于的0到24的显示-verilog to write a 5 x 5 keyboard scanning procedures, and can be implemented for the use of digital tube display of 0-24
scommtest
- 串口通信，利用verilog语言能够很好的实现串行通信-Serial communication, use verilog language can achieve the serial communication
lab16
- 利用verilog设计一个数字秒表电路。可以通过按键开始计时，计时完毕，清零设定。-Use verilog design a digital stopwatch circuits. Can be key will begin counting is completed, clear the settings.
3FP
- 一个三分频verilog模块，可以用来学习基本结构。-A three points frequency verilog module can be used to study the basic structure.
DIV
- 用verilog语言设计分屏器，本程序分为两部分，一个可以实现任意奇偶分频的设计，一个可以实现任意半整分频的设计-Split screen using verilog language design, this procedure is divided into two parts, one can achieve arbitrary parity crossover design, one can achieve arbitrary dividing half the whole design