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rec
- 串口接收Verilog程序，可通过参数设置波特率，采用16倍采样方法，稳定可靠，可做为模块直接在顶层例化。-Serial receive Verilog procedures, through parameter setting the baud rate, using 16 times the sampling method, stable and reliable, can be used as module directly instantiated at the top level.
light
- VERILOG 实现LED灯的量变，可改变速度-VERILOG quantitative LED lights can change the speed
Low-Error-and-Hardware-Efficient-Fixed-Width-Mult
- VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and m
multipler
- There is a multiplier function circuit.The program language is verilog code. We can include it into our module to use it.It is a simple and useful function.
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
SensorHubDesignFilesSourceCode
- sensor-hub技术是最新出来的技术，目前用在智能手机领域，手机里面的传感器越来越多，这给CPU带来很大的负担，功耗也随之提高。sensor-hub技术出来后，可以有效的解决这个问题，这是运行在lattice FPGA平台上的verilog源代码，欢迎大家一起交流学习，希望能给你带来帮助。-Sensor- the hub is the latest technology, the current use in the field of smart phones, mobile phone i
project3
- verilog 数码管循环显示两位数 可清零-verilog double-digit digital display can be cleared cycle
LEDhuadong
- LEDhuadong，是基于quarterii写的Verilog程序，可以下载到板子上，是一个工程文件-LEDhuadong, is based quarterii write Verilog program that can be downloaded to the board, is a project file
stopwatch_c
- 用Verilog写出来的秒表。可以实现计时、暂停、继续、清零等基本功能。还能实现简单的菜数字游戏。-Written using Verilog stopwatch. Can achieve timing, pause, continue, cleared and other basic functions. Also enables simple dish numbers game.
smg
- 数码管设计：顶层为数码管的封装，用户可自己分配引脚。很实用的Verilog程序。-Digital design: the top of the digital package, the user can assign pin himself. Very practical Verilog program.
multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
Pro3_chessmove
- 用Verilog HDL语言实现在FPGA上编码，在显示器上显示一个16*9的棋盘格，棋盘格可以移动的，每秒左移一个像素。-Implementation of coding in FPGA using Verilog HDL language, display chessboard a 16*9 on the display, checkerboard can move, the left one pixel per second.
SPI-flash
- ST公司的M25Pxx SPI flash memory的verilog仿真模型，该模型准确地描述了SPI flash memory的行为，包括读，写，擦除等操作，可以用来挂在带有SPI接口的soc外部，方便验证SPI接口。 -ST' s verilog simulation model M25Pxx SPI flash memory, the model accurately describes the SPI flash memory behavior, including readi
zedboard
- zynq开发源文件 verilog开发，如何应用zedboard-zynq verilog design ；can help you start your embedded design based on zynq
uart16550_latest.tar
- uart电路实现，verilog编写，可以综合-uart circuit implementation, verilog writing can be integrated
viterbi_decoder_axi4s_latest.tar
- viterbi解码电路，verilog实现，可以综合有使用价值-viterbi decoding circuit, verilog achieve, you can have the use of integrated value
crc-gen
- CRC的verilog电路生成软件，可以直接生成crc的verilog代码-CRC s verilog circuit generation software, you can generate the crc verilog code directly
vga_color_slip
- 使用Verilog完成VGA的驱动和显示，完整的工程，可直接使用-Using Verilog complete drive and VGA display, complete engineering, can be used directly
lcd1602_test
- 使用Verilog语言完成LCD1602的驱动和显示，通过测试，可直接使用。-Using Verilog language LCD1602 complete drive and display, through testing, can be used directly.
ds1302_seg7
- 使用Verilog完成DS1302的驱动，工程已经经过测试，可直接使用。-DS1302 using Verilog complete drive, the project has been tested and can be used directly.