搜索资源列表
ltc5615_pot
- 使用Verilog完成ILC5615的驱动，已经经过测试，可直接使用工程。-Using Verilog complete ILC5615 drivers have been tested can be used directly works.
iic_wr
- 使用Verilog完成对I2C总线的读写操作，已经经过测试，工程可直接使用。-Using Verilog complete I2C bus read and write operations, has been tested and works can be used directly.
11_lcd1602
- 基于verilog的LCD1602代码，可下载直接使用-The LCD1602 based on verilog code, can be downloaded directly to use
ncd2verilog
- ncd文件转为verilog文件的脚本，包括perl脚本和netgen程序，双击实现转换，需要电脑可以运行perl脚本-ncd file into verilog file scr ipts, including scr ipts and perl netgen program, double achieve the conversion, you need a computer can run a perl scr ipt
six_wave
- 产生六种波形的DDS信号发生器，用verilog实现，有modersim仿真程序和结果，产生正玄波，方波，锯齿波，三角波，阶梯波。实现完全可用-the dds can output six signal，write in verilog。
MDIO_CONTROL
- FPGA，verilog语言实现MDIO接口代码，经过实际验证，可放心参考-FPGA, verilog language MDIO interface code, field-proven, reference can be assured
ch1
- verilog 语言编写的微程序控制器的设计，12位微指令，可以执行5条伪指令-Design micro-program controller verilog language, 12 microinstruction can perform five directive
dot_product
- 实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure
vga
- 一个VGA显示的verilog程序，可以在VGA屏幕上显示图片、颜色等，简单修改子模块代码可以显示不同图像-A VGA display verilog program that can display images on a VGA color screen, easy to modify sub-module code can display different images
Booth2_final
- 该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行-This file is booth multiplier verilog code, after the final simulation, can be directly run
counter
- verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.
Traffic-lights
- 基于verilog语言做的一个交通灯，可以直接用，可以烧到板子上-Based verilog language to a traffic light, can be directly used, you can burn the board
PLL4350_CFG
- ADF4350 配置的verilog hdl程序，模块化设计，输入待配置的数据，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置-Allocation of ADF4350 Verilog HDL program, modular design, input the data to be configured, start signal, can automatically generate timing, complete the configu
spi_rtl
- 支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
SPI_MASTER
- 使用verilog实现SPI主机，包括TB程序,通过验证可以使用。-using verilog come ture spi,including tb program ,it s can use .
divider
- 用Verilog实现的除法器，通过了编译和测试，可以放心使用。-Divider implemented using Verilog, by compiling and testing, you can rest assured that use.
fpga-Verilog_traffic
- 使用verilog语言描述交通灯的功能，已通过实验验证，可直接使用-Using Verilog language to describe the function of traffic lights, has been verified by experiments, can be directly used
accsub
- 简单的加法器减法器程序代码，Verilog HDL初学者学习可以使用-Simple adder subtractor code, Verilog HDL beginners can use
students-website-in-JSP--Students3k.com
- In this homework, you will need to compile and simulate a System Verilog program . (Constraint_mode_ex.sv) which implements multiple constrained-random test A more detailed descr iption of the program can be found below: