搜索资源列表
CPU8
- 本源码实现了8为cpu，开发语言为vhdl，里面有详细的文档和vhdl工程源码-the source to achieve the 8 cpu, development language for vhdl. There are detailed documentation and source code works vhdl
SAP-1Cpu
- EDA的课程设计，自己写到PPT，大致讲了用VHDL语言实现简易CPU的设计，有源码
SojournerProgram
- 这里是我在学校时所写的一些程序，其中有些Java程序可能要重新编译一下才能运行，具体如下：C Course Disign——C语言编写的时钟程序Very Simple CPU——CPU仿真工具StudentQuery——基于SQL语言数据库的学籍管理系统Theory of Computation——一些关于计算理论算法的实现，详见内附说明Hotel——酒店管理系统另外还有一些硬件VHDL方面的程序，整理好后会陆续上传-here at school I wrote some of the proc
RISC_8.rar
- 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。,Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
class34
- eda中的8位的CPU设计，电子类专业非常实用！-EDA in eight of the CPU design, electronics professional very useful!
cpu
- 自编简单cpu，想做CPU开发的同学可做参考。-Simple self-cpu, the development of the students want to do CPU can reference.
cpu16
- 实现一个16位CPU。该CPU使用精减指令集，是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
computerc
- VHDL 编写的简单的CPU 输入程序可以进行有优先级的加减与或的计算，包含键盘和数码管的程序-CPU write simple VHDL program can enter a priority level or the calculation of addition and subtraction and that contains the keyboard and digital control of the process
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
alu_all
- VHDL设计的流水CPU,开发环境是quartusII,代码经过验证，完全是自主开发的源码-A CPU designed by VHDL with PIPE
CPU_project
- CPU设计与实践实验源码，工程文件 ise。VHDL代码 可直接运行-cpu project
CPU
- 计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to g
cpu110
- 基本功能的cpu，自定义内存内容~了解CPU运作原理~-design of cpu,VHDL environment~
cpu110
- 基本功能的cpu，自定义内存内容~了解CPU运作原理~-design of cpu,VHDL environment~
CPU_Design
- 基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
VHDL
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
yu
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
cpu2
- 基于vhdl语言的cpu模拟，包含仿真，含所有器件(CPU containing simulation based on VHDL language)