搜索资源列表
ps2
- 数字逻辑电路实验，ps2借口的吉安帕输入输出，采用ALTER DE2—70板-Experiment, the ps2 an excuse Jian Pa input and output of digital logic circuits using ALTER DE2-70 board
VGA_1
- 利用Quartus II开发环境，在DE2-70开发板上控制VGA显示器显示一幅图像，该幅图像能在显示器范围内按指定路线移动！-Quartus II development environment, control DE2-70 development board VGA monitor to display an image, the image display within a designated route mobile!
Timer
- 用verilog语言实现的定时器。在DE2-70开发板上设计，七段数码管分别用于显示时/分/秒，并带有预置时间功能。-Timer verilog language. DE2-70 development board design, seven-segment digital tubes were used to display hours/minutes/seconds, with the function of the preset time.
DE2-70
- DE2-70 FPGA开发板学习实例及代码，Verilog HDL-DE2-70 FPGA development board learning examples and code, Verilog HDL
DecodeHexabc
- Decoder 8bits FPGA for cyclone altera DE2-70
Counter_10
- verilog 计数器，每计数到十清零，可以直接下载到DE2-70开发板-verilog counter
pinpongf16
- FPGA Verilog程序 采用DE2-70 Altrer 实验班实现小球跳动-FPGA Verilog program using DE2-70 Altrer experimental class of small ball beating
DE2_TV
- 基于fpga的视频处理系统，在Altera的DE2-70开发板上实现。-Fpga-based video processing system, the Altera DE2-70 development board to achieve
paobiao
- verilog实现数码跑表，基于ALTERA DE2—70开发板实现验证，其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.
DE2_70_SD_Card_Audio_Player
- DE2-70 SD card player verilog and nios ii code