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code-demo
- HM6264Driver_DS HM6264 RAM的读写驱动程序 S480_Manual_C S480的手动播放范例 (for SACMV26e.lib) SetIOBit SPCE061A 利用C语言进行软件端口位操作范例 ShowsinTable 简易正弦波发生器方案,同时提供全正数的正弦表 SleepTimerWakeup 定时中断唤醒CPU的范例 UARTDemo 使用UART中断方式进行通讯的范例 UARTDouble UART双机通讯范例,采用中断方
allidt_20020616.tar
- idt的双口ram的读写接口程序,verilog 代码,并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
Asynchronous_read_write_RAM
- Dual Port RAM Asynchronous Read/Write 经过modelsim仿真
read_wirte_ram
- FPGA实现双口RAM功能,从而用FPGA实现双控制器间的数据交换-FPGA realization of dual-port RAM functions, the exchange of data between the dual-controller with FPGA
FPGA-TWO-RAM
- 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
yacc.tar
- mips处理器,将指令和数据放到一个双端口ram里存储-mips processor, the instructions and data into a dual-port ram to store
RAM
- 双口RAM Verilog描述 双口RAM Verilog描述-Dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of dual-port RAM Verilog descr iption of
jj
- 本题设计一个数字存储示波器,以Xilinx公司20万门FPGA芯片为核心,辅以必要的外围电路(包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块),利用VHDL语言编程,实现了任意波形的单次触发、连续触发和存储回放功能,并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时,将外部输入信号经信号调理模块调节到A/D电路输入范围,经A/D转换后送入FPGA内部的双口RAM进行高速缓存,并将结果通过D/A转换送给通用示波器进行显示,完成了对中、低频信号的实时采样和高频信号的等效采
verilog_RAM
- verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
dualportram_vhdl
- 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware descr iption language using the dual-caliber RAM block memory initialization
AdualportramtT
- 采用两片AT89S51对双口RAM IDT7132测试试程序,采用串口助手显示接收内容。, -Using the two AT89S51 dual-port RAM the IDT7132 test pilot program, the serial assistant receive content. ,
Example-b4-1
- 利用quartusII开发软件的宏功能模块调用功能,定制了一个双端口RAM。-Utilize quartusII development software macro function module calls a function to customize a dual-port RAM.
rtl
- dual port RAM 4096x16
Test_2_Port_RAM
- Quartus ii双口RAM模块的使用,包括源码、ram时序图以及测试报告-Use Quartus ii dual-port RAM modules, including source code, ram timing diagram and test reports
Example-b4-1
- 1.定制一个双端口RAM,DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程,在Quartus II仿真器中做门级仿真 在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Qua
dual_port_ram
- True dual port ram VHDL implementation
dualporttst-1_1
- interfacing dual port ram in vhdl