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advanced Serial port with verilog
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Tcode is in VERILOG HDL (Hardware descr iption language)
code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
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朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。
-Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
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lcd
显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
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verilog 编写的串口发送和接收模块，能够设定停止位和校验位，并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
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基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial da
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串口驱动程序,利用Verilog语言编写，且已经通过测试，移植性较好-Serial port driver using Verilog language and has passed the test, better portability
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FPGA SPI串行收发数据全双工程序开发，使用Verilog HDL开发语言-FPGA SPI serial port to send and receive data all double engineering sequence development, using Verilog HDL language development
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实现8位串口的接收和发送模块，将串口接收和发送模块分成了几个小模块进行设计。方便之后的bug的修改。(Receiving and sending module of 8 bit serial port)
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FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)
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利用verilog实现串口发送，每次按键一次发送一次数据，按键模块进行了消抖处理(Using Verilog to realize serial port sending. Each button sends one data at a time, and the key module performs buffeting processing.)
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基于FPGA与PC串口自收发通信-Verilog(Self-transceiving Communication Based on FPGA and PC Serial Port-Verilog)
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