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innovateasia2009
- 串口uart的vhdl，verilog，lattic实现原码-The uart serial vhdl, verilog, lattic realization of the original code
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
uart.v.tar
- uart Universal asyncronous receiver and transmitter verilog code
Verilog-Code
- Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
1.UART
- 该代码主要实现UART的串行通信，针对的是RS232芯片，同时包含了verilog和VHDL编写的程序-The code UART serial communication, RS232 chip, also contains a program written in verilog and VHDL
code
- 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
UART_verilog
- UART串口verilog代码-The UART serial verilog code ..........
uart
- uart设计的verilog代码，支持双工的串行传输，兼容synopsis 的DW_uart的编程模型-verilog code uart design, support duplex serial transmission, compatible synopsis of the programming model DW_uart
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
uart2
- 基于Xilinx ISE的uart传输代码，使用verilog语言完成-Based on Xilinx ISE uart transmission code, completed with verilog language.
uart16550.tar
- UART Verilog RTL Code
UART_source_code
- uart verilog code for nexys2 fpga borad
verilog
- lcd1602 12864显示程序代码，串口传输数据代码(lcd1602 12864 code,UART code.)