搜索资源列表
verilog
- 基于QUATEUS2的设计一个8位频率计verilog语言编程-The design is based QUATEUS2 an 8-bit frequency counter verilog programming language
720X576
- 采用Verilog硬件描述语言实现的液晶屏720X576 rgb扫描频率的输出。-Using Verilog hardware descr iption language of the LCD screen 720X576 rgb scanning frequency of the output.
cpld11245
- 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy
verilog2
- 本代码在Quartus II 9.0 (32-Bit)环境编译运行，使用SOPC_NIOSIIFPGA开发板，可作为入门级代码讲解，将50MHZ的频率改为1MHZ，并以此频率为基准计数显示在七段数码管上。（采用verilog语言）-The code in Quartus II 9.0 (32-Bit) environment to run the compiler, the use of SOPC_NIOSIIFPGA development board, entry-level code ca
speaker
- verilog写的电子钢琴，内容简单，但频率与数字间关系的原理详尽，实验通过，供新手学习讨论-write verilog electronic piano, the contents of simple, but the relationship between frequency and number of the principle of detailed experimental passed, new learning
frequencycounter
- 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
xinhao
- 基于verilog的数字信号产生器，包括三角波、方波、正弦波，频率可调。-Verilog-based digital signal generator, including a triangle wave, square wave, sine wave, frequency adjustable.
FTEST2
- Verilog语言，等精度频率计/测脉冲宽/测占空比-Verilog language, and other precision frequency meter/measuring pulse width/measured duty cycle
Frequency-meter
- 用Verilog语言编写的频率计，可以精确到1Hz-Frequency counter with the Verilog language, can be accurate to 1Hz
frequency
- 用verilog编写的频率计项目，能够自动换量程-Written in verilog frequency meter project, to wrap range
Freq_counter_ise12migration
- 用verilog实现的一个频率计数器，可分别在不同的频率下计数（自己设定），里面有几个有用的小模块，分频，计数，显示，同步，进位等-Verilog to achieve a frequency counter, respectively, in different frequency count (set), there are several useful modules, divide, count, display, synchronization, binary, etc.
Verilog-crossover-design
- Verilog分频器设计分频器是FPGA设计中使用频率非常高的基本单元之一-Verilog crossover design
PLJ
- 频率计 verilog语言编写 有三级量程可供选择-Frequency meter
zhu
- 基于FPGA的SPI接口设计，主模式，频率可调，verilog HDL编写-FPGA-based SPI interface design, master mode, adjustable frequency, verilog HDL prepared
PLL_cfg_10M
- ADF4001的配置程序，输入输出为10M，鉴相频率10M，VERILOG-configration programm for ADF4001
pinlvji
- 一个用verilog编写的数字频率计，利用FPGA实现计数功能，其中使用的测周法。-A written with verilog digital frequency meter, use FPGA implementation counting function, wherein the measured circumference method to use.
verilog_i10Mhz
- 10MHZ的频率的程序，验证过可以使用，有需要的可以下载(10MHZ frequency of the program, verify that you can use, there is a need to download)
verilog_i20Mhz
- 20MHZ的频率的程序，验证过可以使用，有需要的可以下载(20MHZ frequency of the program, verify that you can use, there is a need to download)
fredeng
- 用verilg语言实现等精度测量频率，最大可测100m。(Implementation of equal precision frequency measurement with verilg language)
lowpass
- 低通滤波，参数含通带截止频率，阻带截止频率，边带区衰减DB数设置，截止区衰减DB数设置和序列x的采样频率。(Low pass filter, parameters including passband cut-off frequency, stop band cut-off frequency, sideband attenuation DB number, cut-off area attenuation DB number setting and sequence x sampling fr