This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave

此为用verilog hdl编写的FPGAproject 其中A5+工程为带vga显示 分辨率600*800@60HZ 带字母显示（直接将ASCII码输入到寄存器中 窗口大小可调整）；A1工程为软核处理器 可配合使用 实测功能强大-This is written in Verilog HDL FPGAproject the A5+ engineering with VGA display resolution 600*800@60HZ with letters display directly

cordic processor in verilog code is been programmed for fpga. Cordic has rotational matrix with input vectors which can be rotated in phasor plane