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EEthhernet_vet
- Ethernet(以太网)verilog ip core用veriloggHDL语言写的以太网软核，对学习verilog语言与以太网有非常大帮助。 -Ethernet (Ethernet) Verilog the ip core with veriloggHDL language Ethernet soft-core, there is a very big help to learn verilog language and Ethernet.
i2c_master
- I2C master模式的IP core（verilog）-I2C master mode IP core (verilog)
IPCores_iic_8051
- I2C_IP_Core, 使用VHDL 和VERLOG编写，并有文档说明-I2C IP Core, VHDL/Verilog
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
cordic
- Altera 的CORDIC IP核，Verilog HDL-Altera CORDIC IP core, Verilog HDL
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
IPcore
- verilog IP核调用子程序，源码-Verilog IP core call subroutine, the source code
rtl_1795
- Developper:mathswork Arm IP Core Verilog This IP core is an ARM clone. It has the same architecture of ARM v4. Its main feature lists: Not support coprocessor instructions Not support THUMB instruction set All interrupts
LED
- FPGA中实现led流水灯,通过Verilog语言编程，程序中调用了xilinx公司提供的时钟分频IP CORE-This file is to achiece led like water
FFT v1
- IP core fft verilog code example
高大上欧美风商务PPT模板
- JPEG_d IP Core Verilog crypted source