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statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
cordic
- verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
proc_pipe
- A 5 stage pipeline CPU written in verilog codes
dot_product
- 实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure
0340196Lab3
- 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
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- 针对矿浆管道工况调整给泄漏检测带来的干扰，准确提取泄漏信号的特征量是降低泄漏误报、漏报的关键。为此，提出了一种基于经验模态分解（EMD）、Hilbert能量谱与变量预测模型（VPMCD）相结合的泄漏检测方法。该方法首先将压力信号分解成若干个固有模态函数（IMF）之和，然后将IMF分量进行Hilbert变换得到局部Hilbert能量谱，依据能量分布的标准差选择最能准确反映矿浆管道运行工况的局部能量谱作为特征值向量，最后通过VPMCD分类器建立泄漏识别模型。将该方法应用于泄漏检测中，实验结果表明，矿