搜索资源列表
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
rng_opencore
- opencore, random number generator, verilog
lfsr.v.tar
- linear feedback shift register for generator in verilog code for random sequence generation.
prs8
- 伪随机序列verilog 以及 测试程序-Pseudo-random sequence verilog
m-sequence-of-pseudo-random-noise
- 基于verilog 的用于通信系统的m序列伪随机噪声，可综合，我已验证通过。-Based on the verilog for m-sequences of pseudo-random noise of the communication system, can be integrated, I verified through.
lutsr
- verilog design of lut sr random number generator
students-website-in-JSP--Students3k.com
- In this homework, you will need to compile and simulate a System Verilog program . (Constraint_mode_ex.sv) which implements multiple constrained-random test A more detailed descr iption of the program can be found below:
seg_display
- verilog语言编程，通过编程实现伪随机码的产生，程序简单易懂，易上手，带测试平台文件-verilog language programming, programming produced by pseudo-random code, the program easy to understand, approachable, with a test-platform file
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
Sender
- verilog langurage to generate random numbers
基于FPGA的高斯随机数发生器的设计与实现_徐新才
- 介绍了一种利用FPGA硬件平台生成高斯随机数的算法。(An algorithm for generating Gauss random numbers using FPGA hardware platform is introduced)
random_num_gen
- 本人用verilog编写的随机数生成文件，经测试可用。(I am prepared to use verilog random number generator, the test is available.)