搜索资源列表
enc
- HDB3编码器 使用VHDL编制 对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
mp3_decoder
- mp3的VHDL实现，包括HUFFMAN编码器，量化器，子带滤波器．可用来开发：ＦＰＧＡ，ＡＳＩＣ．-mp3 of VHDL, including HUFFMAN encoder, quantizer, subband filters. Can be used to develop : FPGA, ASIC.
AB4F
- FPGA编码器4倍频VHDL程序 对初学FPGA有帮助。-FPGA Encoder 4 multiplier VHDL program to FPGA beginner help.
pie
- pie编码器,将串行数据并行输出的一种常用编码-pie encoder, parallel to serial data output of a common coding
xapp339
- it is NRZ 2 Manchester encoder
control
- Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
rom
- Turbo码编码器的Rom宏模块，此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
RS_Encoder
- its a reed solomon encoder-its a reed solomon encoder.....
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
rsencoder_latest.tar
- reed solomon encoder (255,239) verilog source code
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
div63
- 可以对增量式编码器输出的AB相信号进行整数分频。有一个简单的通讯接口，可设定分频大小。 -Incremental encoder can output an integer number for AB believe frequency. There is a simple communication interface, can set the size frequency.
550vvhdll0
- 50个VHDL常用的模块，包含计数器器，译码器，编码器，锁存器等等，可供参考 -50 VHDL commonly used modules, including the counter, decoder, encoder, latches and more is available for reference
8-3-Encoder
- VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
BCD-ENCODER
- VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
BIN-ENCODER
- VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
PARITY-ENCODER
- VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment
Run-length-encoder
- vhdl code for run length encoder
encoder
- Encoder is written in VHDL. This is simulated using ISIM and synthesized with ISE