搜索资源列表
FFT16
- 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
cpu的VERILOG描述
- RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL descr iption
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
jtag_verilog
- verilog 实现的jtag ip模块 包括了测试程序-Verilog achieve the JTAG ip modules including test procedures
ISE_chinese
- 通俗的介绍了ise的使用方法，对vhdl和verilog开发的初学者来说是不错的选择-popular introduction to the use of the method ideally, the VHDL and Verilog development of the newcomer is a good choice
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
11.2
- 推荐下载,verilog处理器设计实例.体现了结构描述和寄存器传输描述的应用 -recommend downloading Verilog processor design examples. Reflect the structure descr iption and register transfer described in the Application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
5.8
- 还是一个verilog原代码,可以在modelsim下运行,强烈推荐下载-or a Verilog source code can be run in modelsim strongly recommend downloading
rs-codec-8-16
- 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
allidt_20020616.tar
- idt的双口ram的读写接口程序，verilog 代码，并且有测试文档-Employing a dual-port ram reader interface program, Verilog code, and a test document
verilog_lcd
- 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
uartvhrilog
- This Verilog HDL descr iption implements a UART.
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption
gatediscrip
- 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL descr iption
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
demultiplex
- 是用verilog写的,解复接程序,可以把复接的反过来,一般用在解码程序中!-verilog is written, Demultiplexer procedures can multiplexing the contrary, generally used in the decoding process.
performance
- 用verilog编写的程序,用来计算误码率的,可以在编码和解码过程中用的到的!-verilog prepared using the procedures used to calculate the error rate. the encoding and decoding process used in the!
an391_performance_checksum
- checksum fpga verilog
Verilog HDL 语言编程 RS(204,188)译码器的设计
- Verilog HDL 语言编程 RS(204,188)译码器的设计源码