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用cpld实现曼彻斯特编码2
- 此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。-this procedure code decoder VHDL hardware is used to prepare the language.
MPSK调制与解调VHDL程序与仿真
- MPSK调制与解调VHDL程序与仿真,具有很高的参考价值!!vhdl代码!-MPSK modulation and demodulation process and VHDL simulation, high reference value! ! VHDL code!
crc上传程序
- 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
ccmulVHDL
- vhdl语言编写的复数乘法运算器原代码，采用定点运算，并将复数乘法转为实数运算。-VHDL language in the plural multiplication with the original code using fixed-point computation. will the plural multiplication to real operations.
code
- 实现通信中常用的各种编码方式的vhdl源代码，经过实际验证过
伪随机序列
- 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
bpsk1.rar
- 介绍qpsk调制的代码！初学者可以参考参考！比较简单.,Introduction QPSK modulation code! Beginners can refer to reference! Relatively simple.
runnianpanding
- 数字自动电子日历中的闰年判断代码 ，闰年二月为29天-Digital Automatic electronic calendar to determine the code of a leap year, leap year in February for 29 days
sfs
- DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DDATA START: MOV AX,DDAT
hdl
- 在EDK的环境下的嵌入式源代码，EDK初级使用实例！方便初学者的使用！-EDK environment in the embedded source code, EDK primary use case! To facilitate the use of beginners!
Baseband_line_code
- 本课程设计完成了基带线路码产生电路的设计，数字基带信号的传输是数字通信系统的重要组成部分之一。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。为使基带信号能适合在基带信道中传输，通常要经过基带信号变换，这种变换过程事实上就是编码过程。本些课题实现了这样的编码过程。-This course is designed to use VHDL hardware descr iption language completed the base-band circuits hav
BCHbch
- BCH编码 实现BCH信道编码功能 实现BCH信道编码功能-BCH code BCH code BCH code BCH code BCH code BCH code BCH code
control
- Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
ss
- vhdl code for parallel in parallel out
ldpc7_3
- the attached file consists of LDPC code (7,3). this code can be easily implemented on fpga kit(sparten-3)
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
conv.vhd
- 卷积编码的VHDL代码，公司内部资料，不是个人随便编写的-VHDL code of convolutional encoding
verilog
- source code for USB 2.0 fonction core in verilog
e1framerdeframervhdl
- this a vhdl code for e1 framing deframing -this is a vhdl code for e1 framing deframing
DDS
- 基于DDS原理，利用VHDL语言进行正弦波、三角波、锯齿波、矩形波等波形的发生。包括完整代码和QUARTUS II工程。-Based on DDS principle, the use of VHDL, sine, triangle, sawtooth, square wave waveform occurs. Including the complete code and QUARTUS II project.