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ch17_I2C
- I2C总线协议，可以在quartus上仿真综合，通用性比较好-I2C bus protocol, the simulation can be integrated in quartus, better versatility
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
emif_tt
- 实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding
DDS
- 基于DDS原理，利用VHDL语言进行正弦波、三角波、锯齿波、矩形波等波形的发生。包括完整代码和QUARTUS II工程。-Based on DDS principle, the use of VHDL, sine, triangle, sawtooth, square wave waveform occurs. Including the complete code and QUARTUS II project.
digital-down-converter-ddc
- 这是用VHDL语言写的数字下变频模块，包含整个工程文件，数字下变频是软件无线电中的关键技术，可以直接用Quartus II打开。-this is a module of DDC(Digital Down Converter) with VHDL, it includes the whole project,you can open it with Quartus II directly.