用于FPGA与232通信的编程设计，用VERILOG语言编写的，在ISE中仿真-232 communications for FPGA programming and design, using the VERILOG language in ISE Simulation

用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d-Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding