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crc上传程序
- 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
伪随机序列
- 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
BCHbch
- BCH编码 实现BCH信道编码功能 实现BCH信道编码功能-BCH code BCH code BCH code BCH code BCH code BCH code BCH code
ldpc_c_code
- LDPC码在基于BP (Belief Propagation) 的迭代译码相结合的条件下具有逼近Shannon 限的性能，是继turbo 码后在纠错编码领域又一重大进展。压缩文件中给出了LDPC在高斯信道下的c程序。-LDPC codes based on BP (Belief Propagation) Iterative Decoding of combining conditions with performance approaching Shannon limit on the heel
verilog_scramble.v.tar
- 扰码程序，利用Verilog语言实现，适合各种通信系统的扰码。-scramble code,verilog hdl,adapt to many communication systems
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
verilog
- source code for USB 2.0 fonction core in verilog
C6474L_EVM_RTL
- TI C6474评估板的fpga源代码，初始化板子必备代码，Verilog HDL硬件语言编写。-TI C6474 evaluation board fpga source code, the code necessary to initialize the board, Verilog HDL hardware language.
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code
6IIS.tar
- IIS接口的verilog代码，用verilog编写，片上系统SOC源代码分析的IIS接口代码，总线是wishbone-IIS interface verilog code