搜索资源列表
fpq
- ISP实验分频器源程序，用VHDL写的，在x3s200an芯片上编译的-ISP prescaler source experiment, using VHDL written in compiled x3s200an chip
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
divideclk
- 一个简单的由vhdl代码描述的分频器模型-it is code writing by vhdl,and it is used for divede clk
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
fenpin
- 用VHDL写的一段很小的任意整数分频器，可以设置任意整数数值，来获得所要的分频值-Use VHDL to write for some small arbitrary integer divider can be set to any integer value, so as to obtain the desired divider value
vhdl--of--traffic-light
- 十字路口的交通灯vhdl控制程序，其中包括分频器、交通灯控制器和主程序三部分。-Crossroads of traffic lights the vhdl control procedures, including the three parts of the divider, traffic light controller and main program.
2.5fenpin
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
fenpinqi
- 基于vhdl语言编写的分频器程序，可实现五十分频。-Based divider vhdl language program, can achieve five very frequently.
ise
- 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)
分频显示
- VHDL实验中，实现分频与数码管显示。掌握BCD-七段显示译码器的功能和设计方法； 掌握用硬件描述语言的方法设计组合逻辑电路——BCD-七段显示译码器。(In the VHDL experiment, frequency division and digital tube display are realized.)
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6