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adder17
- 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and
adder
- 4位二进制数比较器，将两个4位二进制数进行比较-4-bit binary comparator, two four binary comparison
chengxu
- 二进制加法程序:两个多字节的二进制数分别放在以ADD1和ADD2为首地址的存贮单元中，两个数的字长度放在CONT单元中。最后相加结果放在以SUM为首地址的单元中。所有数的低字节在前，高字节在后。-Binary adder program: more than two-byte binary number on the ADD1 and ADD2 the first address of the storage unit, two word length on the CONT unit. Fin
adder
- 二进制加法器流水灯，发上来给大家看看，互相学期吧-Binary adder water lights, made up for everyone to see, each semester,
qjq
- 基于VHDL的全加器程序，用门电路实现两个二进数相加并求出和的组合线路，就是求二进制数矢量加法的。-Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
kebianjishuqi
- Verilg HDL语言编写实现进制计数器切换，包括模9、模6、模4、和模8加法计数器，通过按键输入，消抖，数码管显示。开发环境：ISE14.7-Verilg HDL language to achieve binary counter switch, including die 9, die 6, die 4, and die 8 adder counter, through the key input, eliminate jitter, digital display. Developme
BINadd
- 二进制加法原理 学习， proteus模拟原理图。(Binary addition principle learning)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve