搜索资源列表
在ISE下调用计数器IP核
- 非常简单的计数器，在ISE下调用计数器IP核，使用verilog开发得到的。-Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
digitalclock
- Verilog数字时钟 实现24小时的监控，用七段码显示出来，包含时序图等 在ISE下仿真-digital clock Verilog
sdram
- 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware descr iption language
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
DigitalWatch
- 用verilog数字钟，并且在ise上验证，可以显示分秒，并且可以对分和秒进行调整-Verilog digital clock, and verified in ise, can display every minute, and you can adjust the minutes and seconds
LED_TEST
- Verilog的LED闪烁程序，xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
CRC16_8
- 利用ISE软件采用Verilog HDL语言编写CRC码，每时钟处理8bit数据，在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
adc0809
- ADC0809转换器的verilog版本,运用在ISE上，直接可用（注意没有考虑频道问题），结果显示在数码管里（十进制）-Verilog version ADC0809 converters, used in the ISE, directly available (note does not consider channel problems), the results are displayed in the digital tube (decimal)
counter2
- 附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
i2c_lightsensor
- 用Verilog HDL编写的光敏传感器AD/DA程序，AD结果显示在LCD上，DA结果控制LED的亮度，相关软件：ISE Design suit，硬件：xilinx FPGA开发板-Verilog HDL prepared with light sensors AD/DA program, AD results are displayed on LCD, DA of controlling LED brightness, software: ISE Design suit, hardware:
booth.tar
- Booth algorithm multiplier this project design booth multiplier by verilog language. you can open it by ISE and simulate.
clk_div3
- 基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者-Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners
shiyan2
- Verilog HDL实现十进制计数器,FPGA ISE开发环境- Verilog HDL decimal counter
黑金Sparten6开发板Verilog教程V1.6
- 黑金xilinx ise fpga verlog 教程(Black gold Xilinx, ise, FPGA, verlog tutorials)
Multiplier
- fpga门电路实现的8位乘法器, verilog 语言编写，ise平台(implementation of multipler)
ddr3_test
- ddr3相关代码和基于ISE仿真调试，板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
i2s_top
- i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)