搜索资源列表
calculator
- C语言编写的计算器，有界面，能在win-TC下运行，实现了简单的加减乘除等功能。-A calculator that use win-TC development environment,it can be used add , sub ,mul , and div.
mul
- 二分法求大整数相乘，快速便捷。很好的源代码，可以用来学习，直接用于工程也是可以的-Dichotomy for large integer multiplication, quickly and easily. Good source code, can be used to study, can be directly used for projects of
Mul
- 输入多项式的系数和幂，进行简单的四则运算-Input polynomial coefficients and power to carry out simple arithmetic
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to
MUL
- 8-bit modified Booth s algorithm multiplier
mul
- VC环境下实现32位无符号数乘32位无符号数-asm in VC
mul
- MSP430 16x16=>32 multiply //long mul16(register int x, register int y)
mul
- 一般c++的Int型变量为4个字节，做数字比较大整数的阶乘会溢出，本程序利用数组实现大数字的阶乘且可以更改数组的长度-General c++ of the Int variable is 4 bytes, so the number will be relatively large factorial integer overflow, the process utilizes an array to achieve great numbers factorial and can change
mul
- 两个数相乘，实现十进制数相乘的实验，被乘数和乘数均以ASCII码形式存放在内存中-Multiplying two numbers and achieving the decimal multiplied by the number of experiments, multiplicand and the multiplier are the form of ASCII codes stored in memory
booth
- this implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.-this is implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.
calculator.java
- this program works the calculator function.by getting two initial values and perform either add,sub,mul,div according to the option selected in the run time-this program works the calculator function.by getting two initial values and perform either a
SolvePALM
- 很有用的增广拉格朗日乘子法Matlab源码-useful laglange mul. matlab code
CPU
- 使用vhdl实现一个简易的cpu包含and or xor add sub mul 指令-Achieved using a simple vhdl cpu contain and or xor add sub mul instruction
Verilog-shift-mul
- FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘非函数调用-FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication non- function call
mul.fliter
- 用MATLAB实现了多相滤波器的仿真，MATLAB中C语言的实现 -The MATLAB simulation of polyphase filter, the MATLAB realization of the C language
MUL
- 实现了大数之间的减法运算，主要运用数组将大数存储在计算机中然后实现运算-Realized the subtraction of large numbers between the main array will use large numbers stored in the computer and then implement the operation