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32counter
- 用VHDL语言设计一个32位二进制计数器并进行功能仿真 2.用VHDL语言设计一个8位数码扫描显示电路 -A 32-bit binary counter design using VHDL language and functional simulation using VHDL language design an 8-bit digital scanning display circuit
4_bit_counter
- 4位计数器 vhdl 源码 采用最少晶体管实现逻辑-4-bit counter
Digital-system-EDA
- 四位二进制数可预置可逆计数器设计 学习使用MAX+PlusⅡ文本编辑器的模板输入方法,熟悉常用语句的语法现象，掌握VHDL功能描述和结构描述的方法。-Four binary number can be preset the reversible counter design learning using a text editor MAX+Plus Ⅱ template input method, familiar with common statement syntax phenomenon
cnt10
- 基于vhdl的十进制计数器的设计，有计数的功能，是最基础的vhdl模块- Decimal
100jinshuqi
- 100分频计数器，已验证，作为vhdl初学者借鉴，也可在源程序的基础上进行修改-100 binary divider counter
jishuqi
- 交通灯计数器设计，VHDL文件，搭载后续的文件程序可以构成完整交通灯程序。-Traffic light counter design, VHDL files, program files can be equipped with up to form a complete traffic lights.
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
Counter
- 用VHDL设计具有清除端、使能端，计数范围为0-999的计数器设计。输出为8421BCD码-VHDL design with a clear end to enable the end, the design for the counter counting range 0-999. 8421BCD code output
counter
- 自己设计的一个小计数器。应用vhdl语言。-Their design a small counter. Application vhdl language.
Count10PVHDL
- 十进制计数器，用VHDL语言写的，编译环境是ISE13.4。里面有自己写的文档，简单介绍了一下流程，适合初学者。-Decimal counter, written in VHDL language, compile environment is ISE13.4.The inside have their own written document, introduced the process simple, suitable for beginners.
count
- 基于vhdl语言设计实现的计数器程序，可实现模为10.12等等的计数器。-Vhdl language-based design and implementation of a counter, which enables the mold to 10.12 etc. counter.
shiyan2
- 含异步清0和同步时钟使能的加法计数器的设计，可以从0加到99，使用VHDL语言-Cleared containing asynchronous and synchronous clock enable the addition of counter design, added to 99 can range 0, the use of VHDL language
sub
- vhdl实现的计数器，可正向计数或逆向计数，周期为60-vhdl realized counter, it can count forward or backward, a loop is 60
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
ise
- 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)
counter4b
- Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)