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multiper
- 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
xilinx_sdcontroller
- xilinx公司的sdram控制器代码及说明文件-sdram controller of xilinx, codes and notes
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
picieee.tar
- The Synthetic PIC is a synthesizable VHDL descr iption of the basic Microchip PIC 16C5X microcontroller. It is written in the ViewLogic VHDL environment (Workview PLUS 5.2). It has successfully been synthesized to the XC4000 family, although
SinusGen1
- sine wave vhdl code that generates sine wave output using logibox in xilinx
AM_VHDL
- AM Demodulator using VHDL for Xilinx FPGA. ISE software
jj
- 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采
spar6
- pcie xilinx 接口文件,vhdl语言编写-pcie xilinx interface file,writen with vhdl
delight22
- 速度监控器，按键切换速度，数码管显示，若快到临界速度则闪烁。ISE，Xilinx，VHDL-The speed monitor, the key switching speed, digital display flashes if approaching the critical speed. ISE, Xilinx, VHDL
Plasma_Cpu_r10.tar
- Plasma CPU: VGA coded with C and VHDL in Xilinx FPGA
8-3-Encoder
- VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
BCD-ENCODER
- VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
BIN-ENCODER
- VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be
mealy_state_machine_vhd
- vhdl fpga statmachine
E4_6_FirIpCore
- 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)
5_uart_test
- 基于xilinx的Artix7实现UART通信(UART communication based on Xilinx Artix7)
6_eeprom_test
- 基于xilinx的Artix7实现EEPROM的读写(Reading and writing of EEPROM based on Xilinx Artix7)
12_hdma_in_out
- 基于xilinx的Artix7实现HDMI的输入输出(Xilinx based Artix7 implementation of HDMI input and output)
9_ethernet_1g_100M
- 基于Xilinx的Artix7实现千兆以太网的RGMII接口通信(RGMII interface communication for Gigabit Ethernet based on Xilinx Artix7)