搜索资源列表
44
- 加法器测试平台，具有键盘输入，屏幕显示功能-Adder test platform with a keyboard input, screen display
mul
- 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
VHDL
- VHDL. Realization of multi-digit adder
VHDL
- A Full adder using half adder unit in vhdl
full_aller
- 这是基于VHDL的一位全加器设计的程序，分析过程全面-This is based on a full adder VHDL design process, a comprehensive analysis process
adder
- 基本组合电路 含异步清零和同步时钟的加法计数器-Basic combinational circuits with asynchronous clear and the addition of synchronous clock counter
fadd16
- 实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 -Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.
adder
- 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
VHDL
- 加法器、寄存器、半加器、译码器的硬件描述语言的描述-describe summator ，register，half adder,decoder with VHDL
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
qjq
- 基于VHDL的全加器程序，用门电路实现两个二进数相加并求出和的组合线路，就是求二进制数矢量加法的。-Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.
jiafaqi
- 一位全加器的VHDL程序，上学时实验用的，很简单的，初学者可以-A full adder VHDL program, school experiment, very simple, beginners can look
Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
adder
- 全加器：Powerpoint课件示例支持，典型组合逻辑原理图输入设计-full adder design with VHDL
VHDL-Carry-Save-Adder
- VHDL CARRY SAVE ADDER 4,8 BIT DATAFLOW 26,32 BIT STRACTURAL DESIGN
fast-carry-adder-4d
- VHDL实现的快速四位加法器，就是这样，嗯，适合入门-VHDL achieve rapid four adders, exactly, ah, suitable for entry
carry-look-ahead
- it's implementation for carry lookahead adder in vhdl
Adder
- VHDL code for 4bit adder and full/half adders