基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file

Verilog codes for cache memory with direct mapping and write back policy.

A direct mapping cache memory with write back policy written in verilog.