搜索资源列表
I2Cdesign.rar
- I2C总线Verilog源代码描述，ModelSim仿真,I2C bus Verilog source code descr iption, ModelSim Simulation
JTAG-TAP.zip
- JTAG TAP controller verilog source code,JTAG TAP controller verilog source code
zlg_avalon_ps2mouse.rar
- 周立功SOPC 嵌入式系统实验教程书籍配套光盘 PS2鼠标驱动代码,Ligong week experimental course SOPC embedded systems supporting CD-ROM books PS2 mouse driver code
altera_avalon_cfi_flash.rar
- 周立功SOPC 嵌入式系统实验教程书籍配套光盘 FLASH驱动代码,Embedded Systems Week Ligong SOPC experimental FLASH Tutorial CD-ROM drive books matching code
code.rar
- 使用状态机设计一个5位序列检测器。从一串二进制码中检测出一个已预置的5位二进制码,The use of state machines to design a sequence detector 5. From a string of binary code to detect a preset binary code of 5
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
IIR
- 利用dsp builder设计的IIR滤波器，已经验证完全可以使用，只需要把其中系数改变。内含VHDL代码-Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.
FPGA_interleaver
- 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
multiper
- 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
i2s_rel1_2
- I2S verilog HDL code including test environment
gh_timer_8254_081608
- Timer 8254 Verilog source code
8051_ip_core
- 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
dianti
- 六层电梯，实现优先级响应，同方向先响应，具体请看源代码-Six-storey elevator to achieve priority response, with the direction of first response, details, please read the source code
codeloc1k
- 实现电子密码锁的各项功能,经过编译和仿真-Electronic code lock of the function, the compiler and simulation
vhdl
- usb rtl code, to fpga or asic
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
FFT1024
- System generator code for fft implementation. Pls enjoy it
code
- This code for ASCII ALTERA
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
基于vhdl的出租车计价器
- 对vhdl的出租车计价器的设计，自己编写的，有详细的解释和说明，论文附有代码(Taximeter on the design of VHDL, written by itself, there are detailed explanations and notes, papers with code)