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RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
computerc
- VHDL 编写的简单的CPU 输入程序可以进行有优先级的加减与或的计算，包含键盘和数码管的程序-CPU write simple VHDL program can enter a priority level or the calculation of addition and subtraction and that contains the keyboard and digital control of the process
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
CPU_project
- CPU设计与实践实验源码，工程文件 ise。VHDL代码 可直接运行-cpu project
CPU
- 计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to g
CPU_Design
- 基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
VHDL
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
yu
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
cpu2
- 基于vhdl语言的cpu模拟，包含仿真，含所有器件(CPU containing simulation based on VHDL language)