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asic_final
- Verilog 程序 实现一个简单的语音信号增强DSP设计 分为左右声道-To realize a sound de-nosing dsp using verilog
zixiechengxu
- 用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，-Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures
FPGA_DSP
- 《FPGA数字信号处理与工程应用实践附光盘》配套源代码-FPGA DSP and their applications with verilog HDL