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miaobiao 用verilog VHDL描写的秒表程序
- 用verilog VHDL描写的秒表程序，可以显示百分秒，秒和分。-Verilog VHDL with the descr iption of a stopwatch program, can display the arc, seconds and points.
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
lfsr
- 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
ask10
- This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can
frequencycounter
- 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
rom_prf_gen
- 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
Verilog
- 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
i2c-IPcore
- 一个I2C 接口的verilog 代码，经过测试，可以用的-Verilog code for an I2C interface, tested, can be used
sourceInsight-lan
- souceinsight软件的语言解析文件，用于高亮关键字，开发浏览代码时，有所帮助。-DeviceIOControl, vc in io shows how to direct the operation of the underlying need friends can learn about.
CAN(OpenCores)
- CAN控制器源码 Verilog-CAN controller source Verilog
My-szz-Verilog
- 用硬件描述语言编写的电子钟程序，并可以在试验箱上面实现的-Electronic clock program using a hardware descr iption language, and can be achieved in the chamber above the
CAN--Verilog-code
- can协议转换控制器的Verilog代码，在Quartus软件上测试通过-The CAN protocol conversion controller Verilog code, through the test on Quartus software
xge_mac_latest.tar
- 用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码-Ethernet controller based on Verilog, can be used directly, all verilog files
verilog_i10Mhz
- 10MHZ的频率的程序，验证过可以使用，有需要的可以下载(10MHZ frequency of the program, verify that you can use, there is a need to download)
verilog_i20Mhz
- 20MHZ的频率的程序，验证过可以使用，有需要的可以下载(20MHZ frequency of the program, verify that you can use, there is a need to download)
fft1024 verilog代码
- fft1024 verilog 代码 可以编译成功 建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)
20 CAN总线实验
- 基于can总线的，Verilog源代码分享，可以在Z7030芯片开发板进行演示。(Based on the CAN bus, Verilog source code sharing, can be demonstrated in the Z7030 chip development board.)