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Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器,并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
shuzizhong
- 在ise平台上用VHDL语言实现数字钟,具有计时和重置时间功能、整点报时功能、闹钟功能,每个功能都使用元件例化的方法,通过顶层文件将每一个模块联系在一起。-On ise platform using VHDL digital clock with timer and reset the time function, the whole point timekeeping function, alarm clock function, each function using the compone
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- 用VHDL语言设计全加器的设计方法,使用元件例化的方法设计多位加法器-VHDL language design full adder design method using component instantiation approach to design multi-bit adder