锁相环是一种反馈电路，其作用是使得电路上的时钟和某一外部时钟的相位同步。PLL通过比较外部信号的相位和由压控晶振（VCXO）的相位来实现同步的，在比较的过程中，锁相环电路会不断根据外部信号的相位来调整本地晶振的时钟相位，直到两个信号的相位同步。-PLL is a feedback circuit, and its role is to make the clock circuit and a phase of external clock synchronization. PLL signal

由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock

锁屏时钟，包含闹钟、亮度、音乐、图片等功能。-ScreenLock Clock，include the function of alarm clock、brightness、music、picture and so on.

通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)