搜索资源列表
codeacq
- 扩频接收机设计实例,vhdly源代码!大家下载下来吧,在ise中调试通过
FPGARS232
- 在ISE上可运行次程序 改程序主要用实现FPGA串口通信
FPGA-OFDM-communication-system
- 基于ofdm系统的各个模块的VHDL程序，软件是用的ISE仿真的。绝对有用。-Ofdm systems based on VHDL program of each module, the software is to use the ISE simulation. Absolutely useful.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
usrp-fpga-mirror
- 通用无线电外设置(USRP)的FPGA源代码-USRP in the FPGA source code
UART
- 使用方法： uart编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: uart programming, copied to the hard drive, open the project file with ISE can
uart_fpga
- 一个完全好用的程序,用ISE 8.2打开就可直接应用-A fully-to-use procedures, with ISE 8.2 can be applied directly to open
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
Example_ISE
- ISE中一个工程例子,有说明,可以参考下-Example of a project in ISE, it has made it clear, you can refer to the following
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
AGC
- 自动增益控制，通过仿真验证，已用到工程中，在ISE中运行实现。-Automatic gain control, through the simulation has been used in projects, run in the ISE implementation.
UART
- 串行接口芯片的设计。本程序是在ISE开发环境中编写的UART串行通信接口。适合初学者的学习。-Serial interface chip designs. The program is written in the ISE development environment in the UART serial communication interface. For beginners to learn.
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
ISE-graphics
- 3D图形，单精度浮点乘法器，单精度浮点除法器，单精度浮点乘累加器-3D graphics,single float pointing multiplier, single float pointing divider,single float pointing MAC
verilog_UART_100MHZ
- 自己写的verilog UART程序，前仿真后仿真，下到板子里都对，ISE的-Verilog UART write your own program, before simulation after simulation, are right next to the plate yard, ISE' s
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
clk_div3
- 自己用xilinx ise编写的分频器程序，可以奇分频偶分频，分频系数可以自己设置。方便产生各种时钟信号-Divider program prepared using the Xilinx ISE, odd even divide divider division factor can set up their own. And convenient produce a variety of clock signal
wave_generator
- 文件里包括了利用xilinx ISE 设计波形发生器所要用到的三角波，正弦波，矩形波rom文件-File including the use of the Xilinx ISE design waveform generator to use the triangle wave, sine wave, square wave rom file
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
lvds
- LVDS的FPGA实现,包括ISE工程和源码，还有一个pdf演示文档-FPGA implementation for LVDS