搜索资源列表
USB2.0_rtl_ipcore_verilog
- 经过门级网单验证的USB2.0 IP核 RTL代码-net after gate-level verification of USB IP Core RTL code
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
bluetooth.tar
- 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.
fpga_mcu_uart
- 用FPGA 开发板 SPARTAN3实现的串口程序，用XILINX 自带的ip核 -Achieved with the FPGA development board SPARTAN3 serial program that comes with the ip nuclear XILINX
ISP1362-IP
- ISP1362的IP核用在USB 控制上可与PC通讯，作为SOPC的IP核-ISP1362' s USB IP core used in the control of communication with PC as the IP core SOPC
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Nios-II
- niosII的ip核的实现原理讲解，讲解的非常详细。-niosII ip nuclear realization of the principle of explanation, to explain in great detail.
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
51
- 完整的8051的IP核，用VHDL语言描述-the ip core of c8051,described in VHDL language
usb1.1_sim_465206689
- usb1.1_sim_465206689 IP核开发以及其调用。-usb1.1_sim_465206689 IP core development, as well as its call.
trans_and_delete
- 1/2,3/4可配置的卷积码编码，其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
usb1_funct
- USB2.0的IP核（详细verilog源码和文档）-USB2.0 IP core (detailed Verilog source code and documentation)
generic_fifos_latest.tar
- FIFO通用，可以尝试一下，很实用的IP核-FIFO generic
CanIPCore
- microblaze软核生成，外设包括IO、timer及can总线控制芯片SJA1000自定义IP核-Soft MicroBlaze generation, including IO, timer and can peripheral bus control chip SJA1000 custom IP core
mi2c
- Mentor Graphics I2C Core 主从模式IP核的仿真。原创的仿真激励，对编程有明确的指导意义，绝对值得你的支持。-Mentor Graphics I2C Core and simulation.Original simulation stimulus,can be a guide to the programmer,definitely worth your support.
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
UART_FIFO
- FPGA，串口调试程序，接收模块，含FIFO IP核-FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)
PG007_Xilinx RapidIO IP阅读笔记
- srio pg007 中文，iP核介绍和仿真步骤(The iP core is introduced and simulation steps)