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uart
- this a Uart source code using Verilog.
uart
- 采用CPLD实现串口通信（Verilog硬件描述语言）
uart
- Uart port 是一段不错的，完全可综合的verilog源码
uart(Verilog)
- RS232的verilog源代码,如果需要的可以
uart
- UART接口的VERILOG代码，经过调试成功！
uart
- 串口通信的接收和发送数据的verilog编程，对每条语句有详细说明其实现的功能。
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
uart
- Verilog实现串口收发数据，包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
FPGA-RS232-verilog
- fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug deb
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
UART
- 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
uart
- verilog写的与电脑通信的uart，我实验过了，一切都很好，工作很好-verilog written communication and computer uart, I had the experiment, everything is very good, very good work
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
UART
- 用verilog编写的UART串口通信程序，经验证误码率为0，系统由ARM控制FPGA的串口进行通信；-Written in verilog UART serial communication procedures, proven error rate is 0, the system controlled by ARM FPGA serial communication
FPGA实现串口解析
- 用verilog语言不同的编写方式来 实现各种复杂串口通讯(use the verilog to uart)
uart
- 一个具有固定波特率的 UART 串口收发器，可以实现 串口收发器，可以实现 9600 波特率的串口通信， 能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC
VERILOG_UART
- Simple implementation of UART on Verilog
UART发送接收奇偶校验
- 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
12345 keyuart
- verilog实现uart串口编程 FPGA板与PC传输数据(verilog uart processing FPGA and PC communication)