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this a Uart source code using Verilog.
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内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
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详细介绍了基于verilog设计uart的原理，并提供源代码，实用性强-Detailed design based on Verilog UART principle, and to provide source code, practical
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带有自适应功能的UART，是用VERILOG编写的源码，包括测试文件，与大家分享-Adaptive function with UART, are prepared using VERILOG source code, including test papers, to share with you
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一个uart的Verilog代码，希望能够帮助你做UART逻辑。-Code about uart. You can use it as an example when desighn UART logic.
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该程序是基于UART的控制，有VHDL和verilog的源码，共有兴趣的朋友参考-The program is based on the UART' s control, there is VHDL and verilog source code, a total interest of a friend reference
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Code VHDL/Verilog for UART
FPGA: Xilinx, Altera-Code VHDL/Verilog for UART
FPGA: Xilinx, Altera...
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使用Verilog编写串口发送16bits，内含补码运算；参数化编写。-verilog uart 16bits transmitter two s complement parameter code
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UART FPGA实现过程文档说明，及VERILOG HDL 代码，希望能帮助有需要的人，-UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you
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a verilog code to receive data in uart standard
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verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
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串口逻辑的verilog实现，输入可以为字节、双字、四字-verilog code for uart
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EP208Q8F17C8芯片的串口通讯程序(uart communication verilog code)
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