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uart
- Verilog实现串口收发数据,包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序,FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
UART
- Verilog实现的UART程序,用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
QPSKmodulationanddemodulation
- 这是一个QPSK比较完整的FPGA工程,是用Verilog语言写的,主要包括调制解调模块。-This is a QPSK FPGA project is written in Verilog language, including the modem module.
uart16550_latest.tar
- UART16550是较为通用的串口协议,压缩包内有4个文件可供选择,直接提供RTL源码,可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.
USB-IPcore-Verilog
- USB IP 核设计,Verilog,ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
RS232-IPcore
- RS232 by verilog,ALTERA 的工程,由几个文件组成,可以参考学习-RS232 by verilog
I2C_highway
- 利用硬件描述语言verilog 按I2C总线协议编写了代码,是一个完整的工程,芯片设计中可以参考-Using the Hardware Descr iption Language Verilog according to the I2C bus protocol to write the code, is a complete project, the chip design can refer to
IIC
- IIC读写发送到PC串口 Verilog 源代码与工程文件(IIC read and write, send to PC serial Verilog source code and engineering documents)
d974d4330bf7
- 这是一个非常完整的qpsk调制解调用fpga实现的工程,在工程中已经能够正常使用,使用的quartus ii 开发,使用Verilog语言,文件中还包含了各种滤波器的系数文件,还有matlab仿真文件,整个工程包含从串并变换,相位映射,到成型滤波,中通滤波,cic滤波,调制,再到解调过成的下变频,匹配滤波,载波提取,位定时,判决,整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implemen
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发,包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)