搜索资源列表
uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
uart2iic
- UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写
demo_24c01a
- 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写
usb
- 实现了USB接口。介绍了如何使用VERILOG语言实现USB的程序设计。
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
HDLC
- hdlc设计，包括flag检测，插0、串并转换等设计，采用verilog编程。-hdlc design, using verilog
RS232CUART
- 详细介绍了基于verilog设计uart的原理，并提供源代码，实用性强-Detailed design based on Verilog UART principle, and to provide source code, practical
cic3_decimator
- 用Verilog语言实现积分梳状滤波器(CIC)设计-Achieve integration with Verilog language comb filter (CIC) design
Veriloghuawei
- 华为典型的verilog程序的设计 很有用-Huawei verilog typical design process is useful
Integral_comb_filter_verilog_design
- 积分梳状滤波器(CIC)verilog设计.rar-Integral comb filter verilog design.rar
GSM_DDC
- GSM中数字下变频器的matlab辅助设计，并可以采用matlab生成verilog代码。-GSM digital down converter in the matlab-aided design, and can be used matlab generate verilog code.
pci-verilog
- USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
dhpi
- 接口设计，描述硬件与fpga的接口程序，使用verilog语言-Interface design, describe the hardware and fpga interface program, use the verilog language
usbjtag
- 用于USB blaster下载线设计的JTAG仿真用的Verilog源码-For the USB blaster download cable design simulation using Verilog source JTAG
code
- <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
Code_NCO.zip
- 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
SystemVerilog for Design(Second Edition)
- 本文档用于使用systemverilog系统硬件描述语言做ASIC设计，深入浅出，易懂(The doc is using systemverilog system harward descr iption language to do ASIC design.The doc is easy to read,for new bird in this fact.)