搜索资源列表
async_fifo2_corrected
- FIFO的部分verilog代码，其余部分我会陆续上传，
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
fifo
- 基于verilog的fifo异步实现的源代码和分析。-fifo
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
spi_cbb
- 基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
tx_interface_project
- 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
fifo
- Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)