搜索资源列表
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
ethmac10_100M
- 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
usb1_funct
- USB2.0的IP核（详细verilog源码和文档）-USB2.0 IP core (detailed Verilog source code and documentation)
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened