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ourdev_187634
- fpga 串口通信 本程序在fpga开发板上实验成功-fpga serial communication program in fpga development board in this experiment was a success
IIC_slave
- IIC_slave硬件的代码,已经经过FPGA验证-IIC_slave hardware code, and has been verified through FPGA
high_speed_data_recovery
- 1. 程序的功能是:高速串行数据的恢复. 2. 其基本原理是:利用过采样,检测串行数据的边沿跳变,然后根据边沿提取处在数据相位正中央相邻的抽样值,将串行数据恢复过来。 3. 此程序是verilog 语言编写,用于xilinx virtexE 系列的FPGA-1. Program functions are: high-speed serial data recovery. 2. The basic principle is: the use of over-sampling to det
Fusion_UART
- 此段程序是基于fusion fpga的,是串口通信的验证程序-This section is based on fusion fpga program, is verification of serial communication program
9600divider
- 任意分频器,可以实现FPGA的CLK分频功能,已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
HDLC_VHDL
- 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructi
FPGA_UART
- 本例用VHDL语言在FPGA上实现UART的控制,包括了波特率发生器,接收器,发送器,奇偶校验模块,以及滤波模块和测试模块,能让您更透彻的了解UART的工作原理。-In this case the FPGA using VHDL language to achieve UART' s control, including the baud rate generator, receiver, transmitter, parity modules, and filtering module
uatr_and_dds
- 实现通过PC来控制fpga发出波形,波的形状和频率可通过PC控制,波形利用dds来发出,这是当时我做的电子测量的课程设计。-Fpga implementation given by PC to control the waveform, wave shape and frequency can be controlled through the PC, waveform using dds to send, this is when I do the electronic measurement
HAMMING_CODE_vhdl
- 用vhdl语言编写的汉明码的发送与接收,并在fpga开发板上实现-With the Hamming code written in vhdl sending and receiving, and fpga development board implementation
fpga_mcu_uart
- 用FPGA 开发板 SPARTAN3实现的串口程序,用XILINX 自带的ip核 -Achieved with the FPGA development board SPARTAN3 serial program that comes with the ip nuclear XILINX
UART
- FPGA实时监测RS232_RX信号是否有数据,若接收到数据,则把接收到的数据通过RS232_TX发送回对方。上位机使用的软件是串口调试助手(多模式课程网站下载)。在代码设计中,数据的波特率是可选的,可以根据需要进行配置,如9600bps,19200bps,38400bps,57600bps或115200bps。发送的数据帧格式为:1位起始位(保持一个传输位周期的低电平),8位数据,无校验位,1位停止位。-The FPGA real monitoring RS232_RX signal whet
UART
- fpga开发板与电脑进行串口通讯,实现了基于FPGA的串口接收发功能-fpga development board with a PC serial communications, FPGA-based serial port to receive hair
pulsewidth4
- 使用FPGA DE2平台 测整形后方波信号的脉宽-FPGA DE2 platform for measuring the plastic rear wave signal pulse width
UART
- FPGA串口通信程序,Verilog HDL语言下的UART串口通信程序-Verilog HDL UART
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
FPGA_uart
- fpga实现串口通信 verilog语言实现 -uart communication using FPGA Verilog language implementation
UART_FOR_Altera
- 用于控制3个独立的全双工传输的UART/RS232接口。该接口由Altera SOPC 实现,开发环境为NIOS II。在Statrix II上工作正常。 每个接口可独立配置为短数据模式和数据流模式。-This C source file is used for controling three UART/RS232 interfaces . These interfaces are implemented by Altera s SOPC module , assembled in a S
clk_test
- UART串口程序,将FPGA数据传到上位机上-UART program,transmitting data from FPGA to PC
UART_TXD_RXD_Verilog
- 开发异步串口FPGA逻辑的说明文档及代码,其中代码用Verilog编写,我就是看这些文档和源码编写了自己的串口程序-uart,txd,rxd ,select baud