采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.

I2C slave IP core，内含此IP core的完整code，详细的式样说明,详细的状态机说明-I2C slave IP core, include complete code of this IP core, and the detailed specification, the detailed FSM.