本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr

用VHDL编写的quartusii平台上的串行EEPROM配置读取的程序。-Quartusii prepared using VHDL platform to read the serial EEPROM configuration procedures.

详细介绍了用QuartusII的使用流程-Described in detail with the use of process QuartusII

在QuartusII中利用niosII构建内核控制一位数码管显示0—F，经过硬件测试。-Use niosII build kernel control a digital tube in the QuartusII 0-F, after a hardware test.