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spi_cbb
- 基于FPGA设计,verilog语言变成的,SPI通用接口模块,顶层已封装成类似标准的FIFO接口;提供仿真文件;仿真器为modelsim10.0c,波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
uart
- 黑金FPGA开发板串口收发程序,其中加入FIFO模块作为输入输出缓冲-Black gold development board FPGA procedures, which joined the FIFO module as input and output buffer
UART_FIFO
- FPGA,串口调试程序,接收模块,含FIFO IP核-FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838
tx_interface_project
- 带FIFO的串口发送模块,简单的FPGA串口发送模块(Serial transmission module with FIFO)