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Verilog
- 直方图均衡化处理,基于FPGA, verilog语言-Histogram equalization, based on FPGA, Verilog language
lmsjunheng
- 信号在传输过程中存在着多路径干扰,根据最小均方误差准则实现时域均衡,达到良好的解复用效果-The existence of multi-path interference signal during transmission, time-domain equalization based on minimum mean square error criterion, to achieve a good effect of the demultiplexed