搜索资源列表
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
usb1_funct
- USB2.0的IP核（详细verilog源码和文档）-USB2.0 IP core (detailed Verilog source code and documentation)
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened