搜索资源列表
Usb_RTL(VHDL_Verilog)
- USBRTL电路的VHDL和Verilog代码-USBRTL Circuit VHDL and Verilog code
EDATA_REG_RISC_2006_6_23_11_58_23_50710591
- vhdl语言,用专门的工具产生的这个文件-VHDL language, using specialized tools of this document
usbvhdl
- usb 代码 用VHDL编写 方便初学者使用 学习 有什么不明白的 大家可以回复 互相交流-usb using VHDL code to facilitate the preparation of beginners to learn what we do not understand each other can return exchange
clkvhdl
- 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
USB
- 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动
usb_xilinx
- usb的接口资料，vhdl
usb
- 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
USB2.0
- UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interfac
usbFPGAconnect
- 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, incl
usb20
- 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
USB
- USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
USB2.0FPGAEXAMPLES
- 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
CY7c68013_fpga_write_sram
- FPGA自FX2 slavefifo中读取数据，写入至SRAM-FPGA since FX2 slavefifo read data, write to the SRAM
2004-02-29_USB_Das_Control_System_dip
- USB的驱动程序 可以方便的使用 已经通过验证-USB driver can easily use has been validated
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
ebook_USB2.0_intel_tranceiver
- High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor
USB2.0code
- 实现USB2.0接口控制的VHDL源代码-USB2.0 VHDL code
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code